tape drive frequency timing generator w173 ..........document #: 38-07313 rev. *b page page 1 of 5 of 5 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? four derived outputs at frequencies specified by hewlett packard computer peripherals bristol/boise (cpb) ? less than 250 ps cycle-to-cycle jitter (13.2 mhz clock excluded derated to 400 ps) ? less than 350 ps absolute jitter ? supports 3.3v operation ? ttl compatible logic: v il = 0.8v max., v ih = 2.0v min., v ol = 0.4v max., and v oh = 2.4v min. ? oe pin has internal pull-up ? 45/55% duty cycle on all outputs ?15 ? output drivers ? accepts 26.5625 mhz input reference ? built-in crystal oscillator circuit. capacitive load presented to the crystal is approximately 14 pf ? outputs designed to drive 30 pf loads ? available in 16-pin soic package functional description the w173 has been defined to meet the timing signal require- ments for hewlett packard cpb tape drive system. s block diagram pin configuration xtal osc refin pll 1 50 mhz 6.6 mhz 13.2 mhz pll 2 oe 10 mhz vdd 6.6mhz gnd 13.2mhz vdd gnd 10mhz 16 15 14 13 12 11 10 vdd x1 x2 gnd oe vdd 50mhz 1 2 3 4 5 6 7 8 9 vdd gnd
w173 ......... document #: 38-07313 rev. *b page page 2 of 5 of 5 note: 1. all inputs, except x1 or x2, have an internal pull-up re sistor. unconnected inputs will assume a logic high condition. pin definitions [1] pin name pin no. pin type pin description oe 5 i output enable: when low, this input signal puts all outputs into a high-impedance state. 13.2mhz 13 o clock output: provides a ttl-level timing signal proportional in frequency to the input signal. for a 26.5625 mhz refer ence, the frequency will be 13.2 mhz. 6.6mhz 15 o clock output: provides a ttl-level timing signal proportional in frequency to the input signal. for a 26.5625 mhz refer ence, the frequency will be 6.6 mhz. 10mhz 10 o clock output: provides a ttl-level timing signal proportional in frequency to the input signal. for a 26.5625 mhz refer ence, the frequency will be 10.0 mhz. 50mhz 7 o clock output: provides a ttl-level timing signal proportional in frequency to the input signal. for a 26.5625 mhz refer ence, the frequency will be 50.0 mhz. x1 2 i external crystal connection: this pin has dual functions. it can be used as an external 26.5625 mhz crystal connection or as an external reference frequency input. x2 3 o external crystal connection: an input connection for an external 26.5625 mhz crystal. if using an external reference, this pin must be left unconnected. vdd 1, 6, 9, 12, 16 p power supply connections : connect both v dd pins to the same voltage, either 3.3v or 5.0v. each v dd pin should have a decoupling capacitor (such as 0.1 f) placed as close to the pin as possible. gnd 4, 8, 11, 14 g ground connections: connect all gro und pins to the common system ground plane.
w173 ......... document #: 38-07313 rev. *b page page 3 of 5 of 5 power supply connections the recommended single voltage power supply configuration for the w173 is shown schematically in figure 1 . these recom- mendations should be followed to both ensure adequate device performance and to cont rol emi. the major consider- ations can be summarized as follows: 1. decoupling capacitor?a 0.1- f decoupling capacitor should be used for each v dd pin to minimize crosstalk be- tween output frequencies. the trace to the v dd pin and to the ground via should be as short as possible. 2. ferrite bead (fb)?a common supply connection should be used for all w173 v dd pins. a ferrite bead should be used on this common supply as shown to remove high frequency system noise. 3. 22- f supply filter capacitor?the 22- f capacitor filters low frequency supply noise that may produce clock output jitter. depending on the particular application, this capacitor may not be required; its use should be considered optional. mounting pads should be implemented in pcb layout. use of this capacitor in production should be determined upon prototype evaluation. 4. pcb power supply traces should be at least 20 mils wide to assure adequate trade impedance recommend power supply schematic?single voltage supply operation. ground connections all ground connections should be made to the main system ground plane. these connections should be as short as possible. no cuts should be made in the ground plane around the clock device since this can increase system emi and reduce clock performance. clock output lines 1. the clock line width should be set to provide a 60 ? trace impedance. this width will vary depending on the pcb ma- terial; the pcb supplier can suggest what width to use for a 60 ? clock line. in general, an 8-mil trace will provide a 60 ?? impedance on a multi-level board. 2. the series termination resistor (sometimes called ?damping resistor?) must be placed in series with the clock line as close to the clock output as possible (within one inch). 3. assume an output resistance from the w173 of 40 ? , choose series resistors appropri ate to the number of driven traces. vdd 6.6mhz gnd 13.2mhz vdd 10mhz vdd 16 15 14 13 12 11 10 9 vdd x1 x2 gnd oe vdd 50mhz gnd 1 2 3 4 5 6 7 8 0.1 f 0.1 f 0.1 f 0.1 f 22 f c1 fb system vdd w173 gnd 0.1 f figure 1. test circuit
w173 ......... document #: 38-07313 rev. *b page page 4 of 5 of 5 absolute maximum ratings [2] stresses greater than those listed in this table may cause permanent damage to the devic e. these represent a stress rating only. operation of the devi ce at these or any other condi- tions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. table 1: parameter descrip tion rating unit v dd , v in voltage on any pin with respect to gnd ?0.5 to +7.0 v t stg storage temperature ?65 to +150 c t b ambient temperature under bias ?55 to +125 c t a operating temperature 0 to +70 c dc electrical characteristics: t a = 0c to +70c, v dd = 3.3v5% parameter description test condition min. typ. max. unit i dd supply current note: clk output = 50.0 mhz output loaded 40 ma v il input low voltage v cc = 5.0v 0.8 v v ih input high voltage v cc = 5.0v 2.0 v v ol output low voltage i ol = 1 ma 50 mv v oh output high voltage i oh = ?1 ma 3.1 v i il input low current 10 a i ih input high current 10 a r p input pull-up resistor v in = 0v 500 k ? c i input capacitance except x1 and x2 6 pf l i input inductance except x1 and x2 7 nh c l xtal load capacitance total load to crystal 12 pf ac electrical characteristics: t a = 0c to +70c, v cc = 3.3v5% [3] parameter description test condition min. typ. max. unit clock outputs t jc output clock jitter, cycle-to-cycle excluding 13.2-mhz output 175 250 ps z o output buffer impedance 40 w d t output duty cycle 45 50 55 % t r rise time between 0.4v and 2.4v 0.8 1.5 4.0 v/ns t f fall time between 2.4v and 0.4v 0.8 1.5 4.0 v/ns t pu stabilization time from power-up to within 0.1% of final frequency 1.5 3.0 ms f a long term output frequency stability over v cc and t a range 0.01 % note: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required. 3. all ac tests are performed using the circuit shown in figure 1 to simulate typical system load conditions. meas urements are taken at the load. threshold voltage for timing measurements is 1.5v.
w173 ......... document #: 38-07313 rev. *b page page 5 of 5 of 5 the information in this document is believed to be accurate in all respects at the time of p ublication but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibil ity for any consequences resulti ng from the use of information included herein. additi onally, silicon laboratories assumes no res ponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon labor atories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other a pplication in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. package drawing and dimensions ordering information ordering code package type w173g 16-pin soic (150 mil) w173gt 16-pin soic (150 mil) - tape and reel lead free cyw173sxc 16-pin soic (150 mil) CYW173SXCT 16-pin soic (150 mil) - tape and reel pin 1 id 0~8 16 lead (150 mil) soic 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 16-lead (150-mil) soic s16.15
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